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ASAHI KASEI
[AK4352]
2V & Low Power Multi-Bit DAC
AK4352
GENERAL DESCRIPTION The AK4352 is an 18bit low voltage & power stereo DAC for digital audio system. The AK4352 uses the new developed Multi-Bit architecture, this new architecture achieves DR=94dB at low voltage operation. The AK4352 includes post filter with single-ended output and does not need any external parts. The AK4352 is suitable for the portable audio system like MD, etc as low power and small package. FEATURES * Multi-Bit DAC * Sampling Rate Ranging: 8kHz 50kHz * On chip post filter * On chip Buffer with Single-ended Output * On chip Perfect filtering 8 times FIR interpolator Passband: 20kHz Passband Ripple: 0.06dB Stopband Attenuation: 43dB * Digital Audio I/F format: 2's compliment, MSB first 18bit MSB justified, 16/18bit LSB justified, I2S * Digital de-emphasis for 44.1kHz sampling * Master clock: 256fs or 384fs * THD+N: -83dB@2V, -89dB@3V * D-Range: 94dB@2V, 96dB@3V * Output Voltage: 1.10Vpp@2V * Low Voltage Operation: 2V (1.8 3.6V) * Low power Dissipation: 6mW@2V * Very Small Package: 16pin TSSOP
DIF0 DIF1
LRCK BICK SDATA
Serial Input Interface 8X Interpolator 8X Interpolator De-emphasis Control
DEM
VCML
Modulator Modulator
LPF
AOUTL
VDD VSS
LPF
AOUTR
PD
Clock Divider
VCMR
MCLK
CKS
VREF
M0040-E-02 -1-
2000/11
ASAHI KASEI
[AK4352]
n Ordering Guide
AK4352VT AKD4352 -40 +85C Evaluation Board 16pin TSSOP (0.65mm pitch)
n Pin Layout
MCLK PD BICK SDATA LRCK DIF0 DIF1 DEM 1 2 3 4 5 6 7 8 16 15 14 CKS VCML AOUTL AOUTR VCMR VREF VDD VSS
Top View
13 12 11 10 9
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name MCLK PD BICK SDATA LRCK DIF0 DIF1 DEM VSS VDD VREF VCMR AOUTR AOUTL VCML CKS I/O I I I I I I I I I O O O O I Function Master Clock Pin Power-Down Pin When at "L", the AK4352 is in power-down mode and is held in reset. The AK4352 should always be reset upon power-up. Serial Bit Input Clock Pin This clock is used to latch audio data. Audio Data Input Pin L/R Clock Pin This input determines which audio channel is currently being input on SDATA pin. Digital Input Format Pin These pins select one of four input modes. De-emphasis Enable Pin When at "H", de-emphasis of fs=44.1kHz is enabled. Ground Pin Power Supply Pin Reference Voltage Input Pin Normally connected to VDD. Rch Common Voltage Pin Rch Analog Output Pin Lch Analog Output Pin Lch Common Voltage Pin Master Clock Select Pin "L": 256fs "H": 384fs
Note: All input pins should not be left floating. M0040-E-02 -22000/11
ASAHI KASEI
[AK4352]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V;Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Note 1. All voltages with respect to ground. Symbol VDD IIN VIND Ta Tstg min -0.3 -0.3 -40 -65 max 4.6 10 VDD+0.3 85 150 Units V mA V C C
WARNING: Operation at or beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V;Note 1) Parameter Power Supply Voltage Reference Symbol VDD VREF min 1.8 typ 2.0 max 3.6 VDD Units V V
(Note 2)
Note 1. All voltages with respect to ground. Note 2. Analog output voltage scales with the voltage of VREF. AOUT (typ.@0dB)=1.10Vpp*VREF/2.
*AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
M0040-E-02 -3-
2000/11
ASAHI KASEI
[AK4352]
ANALOG CHARACTERISTICS (Ta=25C; VDD=2.0V, VREF=VDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data; Measurement frequency=10Hz 20kHz; RL 10k; unless otherwise specified) Parameter min typ max Units (Note 3) Dynamic Characteristics THD+N (0dB Output) -83 -74 dB Dynamic Range (-60dB Output, A-weight) 88 94 dB S/N (A-weight) 88 94 dB Interchannel Isolation 90 100 dB DC Accuracy Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift 60 ppm/C Output Voltage (Note 4) 1.02 1.10 1.18 Vpp Load Resistance 10 k Power Supplies Power Supply Current
Normal Operation ( PD = "H") VDD Power-Down Mode ( PD = "L") VDD Power Dissipation (VDD) Normal Operation Power-Down Mode Power Supply Rejection (Note 5) 10 6.0 20 50 50 9.4 100 A mW W dB 3.0 4.7 mA
(Note 5) -
Note 3. Measured by AD725C (SHIBASOKU). Averaging mode. In case of VDD=3.0V, THD+N: -89dB DR: 96dB (A-weight) S/N: 97dB (A-weight) Note 4. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF. AOUT (typ.@0dB)=1.10Vpp*VREF/2. Note 5. In case of power-down mode, all digital input pins including clock pins (MCLK,BICK and LRCK) are held VDD or VSS.
M0040-E-02 -4-
2000/11
ASAHI KASEI
[AK4352]
FILTER CHARACTERISTICS (Ta=25C; VDD=1.8 3.6V; fs=44.1kHz; DEM= "L") Parameter Symbol min typ Digital filter Passband -0.1dB (Note 6) PB 0 -6.0dB 22.05 Stopband (Note 6) SB 24.1 Passband Ripple PR Stopband Attenuation SA 43 Group Delay (Note 7) GD 14.7 Digital Filter + Analog Filter Frequency Response 0 20.0kHz 0.2
max 20.0 0.06 -
Units kHz kHz kHz dB dB 1/fs dB
Note 6. The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@-0.1dB), SB=0.546*fs(@-43dB). Note 7. The calculating delay time which occurred by digital filtering. This time is from setting the 18bit data of both channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta=25C; VDD=1.8 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Symbol VIH VIL Iin min 75%VDD typ max 25%VDD 10 Units V V A
M0040-E-02 -5-
2000/11
ASAHI KASEI
[AK4352]
SWITCHING CHARACTERISTICS (Ta=25C; VDD=1.8 3.6V) Parameter Symbol min typ 256fs: fCLK 2.048 11.2896 Master Clock Timing Pulse Width Low tCLKL 28 Pulse Width High tCLKH 28 384fs: fCLK 3.072 16.9344 Pulse Width Low tCLKL 23 Pulse Width High tCLKH 23 fs 8 44.1 LRCK Frequency (Note 8) Serial Interface Timing BICK Period tBCK 312.5 BICK Pulse Width Low tBCKL 100 Pulse Width High tBCKH 100 BICK rising to LRCK Edge (Note 9) tBLR 50 LRCK Edge to BICK rising (Note 9) tLRB 50 SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Reset Timing PD Pulse Width (Note 10) tRST 300
Note 8. Refer to the operating overview section "Audio Data Interface". Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4352 can be reset by bringing PD = "L" to "H" only upon power up.
max 12.8
19.2
50
Units MHz ns ns MHz ns ns kHz ns ns ns ns ns ns ns ns
n Timing Diagram
LRCK
50% VDD tBLR tLRB tBCKH tBCKL 50% VDD tSDS tSDH 50% VDD Audio Data Input Timing tRST
BICK
SDATA
LSB
PD
25%VDD
Reset Timing
M0040-E-02 -6-
2000/11
ASAHI KASEI
[AK4352]
OPERATION OVERVIEW n System Clock
The external clocks which are required to operate the AK4352 are MCLK (256fs/384fs) LRCK (fs), BICK (32fs ). The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The frequency of MCLK is determined by the sampling rate (LRCK) and CKS pin. Setting CKS= "L" selects an MCLK frequency of 256fs while setting CKS= "H" selects 384fs. When the 384fs is selected, the internal master clock becomes 256fs(=384fs*2/3). Table 1 illustrates standard audio word rates and corresponding frequencies used in the AK4352. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4352 is in normal operation mode ( PD = "H"). If these clocks are not provided, the AK4352 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4352 should be in the power-down mode( PD = "L"). As the AK4352 includes the phase detection circuit for LRCK, the AK4352 adjusts the phase of LRCK automatically when the synchronization is out of phase by changing the clock frequencies. Therefore, the reset is only needed for power-up.
LRCK (fs) 32.0kHz 44.1kHz 48.0kHz
CKS= "L": 256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK CKS= "H": 384fs 12.2880MHz 16.9344MHz 18.4320MHz
BICK (64fs) 2.0480MHz 2.8224MHz 3.0720MHz
Table 1. Examples of System Clock
256fs or 384fs
MCLK
2/3
H L
256fs
CKS Figure 1. Internal Clock Circuit
M0040-E-02 -7-
2000/11
ASAHI KASEI
[AK4352]
n Audio Serial Interface Format
The AK4352 interfaces with external system by using SDATA, BICK and LRCK pins. Four types of data format are available and one of them is selected by setting DIF0 and DIF1. Format 0 is compatible with existing 16bit DACs and digital filters. Format 1 is an 18bit version of format 0. Format 2 is similar to AKM ADCs and many DSP serial ports. Format 3 is compatible with the I 2S serial data protocol. In format 2 and 3, 16bit data followed by two zeros also could be input. In all modes, the serial data is MSB first and 2's complement format. DIF1 0 0 1 1 DIF0 0 1 0 1 Mode 0: 16bit LSB Justified 1: 18bit LSB Justified 2: 18bit MSB Justified 3: I2S Compatible BICK 32fs 36fs 36fs 32fs or 36fs Figure Figure 2 Figure 2 Figure 3 Figure 4
Table 2. Digital Input Formats
LRCK
Lch
Rch
BICK SDATA Mode 0 SDATA Mode 1
Don't care 15:MSB, 0:LSB (@16bit Data) Don't care 17 16 15 14 0 Don't care 17 16 15 14 0 15 14 0 Don't care 15 14 0
17:MSB, 0:LSB (@18bit Data)
*Mode 1: BICK needs 36fs or more than 36fs.
Figure 2. Mode 0,1 Timing
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 18bit
15 14 1 0 Don't care 15 14 1 0 Don't care
15
14
17
16
3
2
1
0
Don't care
17
16
3
2
1
0
Don't care
17
16
* BICK needs 36fs or more than 36fs.
Figure 3. Mode 2 Timing
M0040-E-02 -8-
2000/11
ASAHI KASEI
[AK4352]
LRCK
Lch
Rch
BICK SDATA 16bit SDATA 18bit
15 14 1 0 Don't care Don't care 15 14 1 0 Don't care Don't care 15
17
16
3
2
1
0
17
16
3
2
1
0
17
* BICK needs 32fs or 36fs or more than 36fs.
Figure 4. Mode 3 Timing
n De-emphasis filter
The AK4352 includes the digital de-emphasis filter (tc=50/15s) by IIR filter. This filter corresponds to 44.1kHz sampling. The de-emphasis is enabled by setting DEM pin "H".
n Power-down
The AK4352 is placed in the power-down mode by bringing PD pin "L" and the anlog outputs are floating(Hi-Z). Figure 5 shows an example of the system timing at the power-down and power-up.
PD
Internal State D/A In (Digital)
Normal Operation
Power-down
Normal Operation
"0"data GD (1) GD (1) (3) (2) (3)
D/A Out (Analog) Clock In
MCLK,LRCK,BICK
(4)
External Mute
(5)
Mute On
Figure 5. Power-down/up sequence example Notes: (1) Analog output corresponding to digital input have the group delay (GD). (2) Analog outputs are floating(Hi-Z) at the power-down mode. (3) Click noise occures at the edges(" ") of the falling edge of PD signal. (4) When the external clocks(MCLK,BICK,LRCK) are stopped, the AK4352 should be in the power-down mode. (5) Please mute the analog output externally if the click noise(3) influences system application. The timing example is shown in this figure. M0040-E-02 -92000/11
ASAHI KASEI
[AK4352]
n System Reset
The AK4352 should be reset once by bringing PD = "L" upon power-up. The internal timing starts clocking by LRCK "" upon exiting reset.
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board [AKD4352] is available in order to allow an easy study on the layout of a surrounding circuit.
External Clock Reset
1 2 3
MCLK PD BICK SDATA LRCK DIF0 DIF1 DEM
CKS VCML
16 15 14 13 12 10 11 10 9 0.1 10 + + + + 10
AK4352
Top View
AOUTL AOUTR VCMR VREF VDD VSS
+
Lch Out
Audio Data Processor
4 5 6 7
Rch Out
Mode Setting
8
Analog 2V Analog Ground
System Ground
Figure 6. Typical Connection Diagram Notes: - LRCK = fs, BICK 32fs or 36fs, MCLK = 256fs/384fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load.
M0040-E-02 - 10 -
2000/11
ASAHI KASEI
[AK4352]
1. Grounding and Power Supply Decoupling Figure 6 shows the power supply connection example. VDD is supplied from analog supply in system. Decoupling capacitors for high frequency should be as near to the AK4352 device as possible, with the low value ceramic capacitor between VREF and VSS being the nearest. 2. Voltage Reference The differential Voltage between VREF and VSS sets the analog output range. VREF pin is normally connected to VDD. An electrolytic capacitor 10F parallel with a 0.1F ceramic capacitor are attached between VREF and VSS pins. VCML and VCMR pins are a signal ground of this chip. An electrolytic capacitor less than 10F parallel with a 0.1F ceramic capacitor attached between VCML, VCMR pins and VSS eliminates the effects of high frequency noise. Especially, the ceramic capacitor should be connected to these pins as near as possible. No load current may be drawn from VCML and VCMR pins. All signals, especially clocks, should be kept away from the VREF, VCML and VCMR pins in order to avoid unwanted coupling into the AK4352. 3. Analog Outputs The analog outputs are single-ended and centered around the VCML, VCMR voltage. The output signal range is typically 1.10Vpp. If the noise generated by the delta-sigma modulator beyond the audio band would be the problem, the attenuation by external filter is required. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCML, VCMR voltage for 0000H(@16bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCML, VCMR voltage + a few mV.
M0040-E-02 - 11 -
2000/11
ASAHI KASEI
[AK4352]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0 1.10max
16
9 A 6.40.2 0.170.05 0.10.1 Detail A 0.50.2 1.0 | 0.10 0-10
Epoxy Cu Solder plate 2000/11 - 12 -
1 0.220.1
8 0.65
Seating Plane
NOTE: Dimension "*" does not include mold flash.
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment:
M0040-E-02
*4.4
ASAHI KASEI
[AK4352]
MARKING
AKM 4352VT XXYYY
Contents of XXYYY XX: Lot# YYY: Date Code
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
M0040-E-02 - 13 -
2000/11

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